Laboratory for Computer Architecture

Research activities cover computer architectures, software-hardware codesign, parallel processing, embedded systems and programmable logic and radio-frequency identification (RFID).

The main research work is dedicated to short SIMD processing and the integration of these new processing facilities into high-level programming languages. Currently, the most significant activities are development of syntax and semantics extensions to the ANSI C in such a way that we could use short SIMD processing facilities in C programming language and development of its vectorizing compiler which is capable to auto-matically extract short SIMD parallelism from loops. We call it MMC (multimedia C) language. We have also introduced a new data-dependence test for array references with linear subscripts. We have named this test the D-test. It is appropriate for the vectorization for modern SIMD microprocessors and is more accurate than existing tests. The test takes into account the architectural properties of modern SIMD microprocessors and allows the existence of those data dependences in the loops that do not prohibit the vectorization for SIMD microprocessors.

The part of research work is directed toward the development of special computer hardware which, through its programmable ALU, is capable of performing custom selected functions. We are also working on RISC architecture microprocesor named MOVE, and HIP which is programmed with VHDL, and then realized with field-programmable gate array (Xilinx FPGA Virtex I and II). These architecture is also suitable for the embedded system applications.

Lately, the important part of research activities include studies of radiofrequency identification technology (RFID) used in supply chain management, wireless tracking of objects to acquire the information used in classification and prediction models. This part of research includes the use of neural networks, support vector machines and some other methods applicable in design of intelligent RFID systems.

 


Collaborators


Selected References

RISOJEVIĆ Vladimir, AVRAMOVIĆ, Aleksej, BABIĆ, Zdenka, BULIĆ, Patricio A simple pipelined squaring circuit for DSP. V: 29th IEEE International Conference on Computer Design 2011, ICCD 2011, IEEE, cop. 2011

ČEŠNOVAR Rok, BULIĆ, Patricio, DOBRAVEC, Tomaž. Optimization of a single seam removal using a GPU. V: ARABNIA, PDPTA 2011 : proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications, Worldcomp'11, Las Vegas Nevada, USA

CUINAS, Inigo, CATARINUCCI, Luca, TREBAR, Mira. RFID from farm to fork: traceability along the complete food chain. V: PIERS 2011 Marrakesh: proceedings. Cambridge (MA): The Electromagnetics Academy, cop. 2011, str. 1370-1374

BABIĆ, Zdenka, AVRAMOVIĆ, Aleksej, BULIĆ, Patricio. An iterative logarithmic multiplier.Microprocess. microsyst.. [Print ed.], 2011, vol. 35, no. 1, str. 23-33, doi: 10.1016/j.micpro.2010.07.001.

TREBAR, Mira, GRAH, Andrej, ALVAREZ MELCON, Alejandro, PARRENO, Alfredo. Towards RFID traceability systems of farmed fish supply chain. V: SoftCOM 2011. Split: FESB, cop. 2011  

FINŽGAR, Luka, TREBAR, Mira. Use of NFC and QR code identification in an electronic ticket system for public transport. V:SoftCOM 2011. Split: FESB, cop. 2011 

LOTRIČ, Uroš, BULIĆ, Patricio. Logarithmic multiplier in hardware implementation of neural networks. ICANNGA 2011, Lect. notes comput. sci., part 1, str. 158-168
 
BULIĆ, Patricio, GUŠTIN, Veselko, ŠONC, Damjan, ŠTRANCAR, Andrej. An FPGA-based integrated environment for computer architecture. Comput. appl. eng. educ., 2010, str. [1-10], doi: 10.1002/cae.20448.
 
BULIĆ, Patricio, DOBRAVEC, Tomaž. An approximate method for filtering out data dependencies with a sufficiently large distance between memory references. J. supercomput., 2011, vol. 56, no. 2, str. 226-244, ilustr. http://www.metapress.com/content/83812675233tt628/fulltext.pdf, doi: 10.1007/s11227-009-0364-8
 
BULIĆ, Patricio, BABIĆ, Zdenka, AVRAMOVIĆ, Aleksej. A simple pipelined logarithmic multiplier. V: 28th IEEE International Conference on Computer Design 2010, ICCD 2010 : embedded systems. [S. l.]: IEEE, cop. 2010, str. 235-240
 
TREBAR, Mira, STEELE, Nigel C. Application of distributed SVM architectures in classifying forest data cover types. Comput. electron. agric.., Oct. 2008, vol. 63, no. 2, str. 119-130, http://www.sciencedirect.com/science/journal/01681699.
 
TREBAR, Mira, ŠUŠTERIČ, Zoran, LOTRIČ, Uroš. Predicting mechanical properties of elastomers with neural networks. Polymer (Guildf.)., Aug 2007, vol. 48, iss. 18, str. 5340-5347.
 
GUŠTIN, Veselko, BULIĆ, Patricio. Learning computer architecture concepts with the FPGA-based "move" microprocessor. Comput. appl. eng. educ., 2006, vol. 14, no. 2, str. 135-14, doi: 10.1002/cae.20072.
 
TREBAR, Mira. Use of MATLAB neural networks toolbox in a character recognition problem. Comput. appl. eng. educ., Apr. 2005, vol. 13, no. 1, str. 66-71.
 
BULIĆ, Patricio, GUŠTIN, Veselko. An extended ANSI C for processors with a multimedia extension. Int. j. parallel program., 2003, vol. 31, no. 2, str. 107-136, doi: 10.1023/A:1022617308483.
 
BULIĆ, Patricio, GUŠTIN, Veselko. An efficient way to filter out data dependences with a sufficiently large distance between memory references. SIGPLAN not., Apr. 2005, vol. 40, no. 4, str. 51-60.
 
BULIĆ, Patricio, GUŠTIN, Veselko. On the use of the MMC language to utilize SIMD instruction set. Lect. notes comput. sci. 4395, 2007, str. [236]-248
 
BULIĆ, Patricio, GUŠTIN, Veselko. On dependence analysis for SIMD enhanced processors. High performance computing for computational science - VECPAR 2004 : 6th international conference, Valencia, Spain, June 28-30, 2004 : revised selected and invited papers, (Lecture notes in computer science, 3402). 2005, str. 527-540



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