Assoc. Prof. PhD Patricio Bulić
Associate Professor
T: +386 1 479 8255
Office hours: I will be on sabbatical from 1 March through 30 June 2017. During this period the consultation-hours will be cancelled
Room: R2.55

He currently holds the position of associate professor on the Faculty of Computer and Information Science, University of Ljubljana, Slovenia. His research interests include computer architecture and organization, parallel processing, computer arithemtic, embedded systems and digital design.


LOTRIČ, Uroš, BULIĆ, Patricio. Logarithmic arithmetic for low-power adaptive control systems. Circuits Systems and Signal Processing, ISSN 0278-081X, 2016, vol. , no. , str. 1-21,, doi: 0.1007/s00034-016-0486-1.

AVRAMOVIĆ, Aleksej, BABIĆ, Zdenka, RAIČ, Dušan, STRLE, Drago, BULIĆ, Patricio. An approximate logarithmic squaring circuit with error compensation for DSP applications. Microelectronics journal, 2014, vol. 45, iss. 3, str. 263-271.

ČEŠNOVAR, Rok, RISOJEVIĆ, Vladimir, BABIĆ, Zdenka, DOBRAVEC, Tomaž, BULIĆ, Patricio. A GPU implementation of a structural-similarity-based aerial-image classification. The journal of supercomputing, Aug. 2013, vol. 65, no. 2, pp. 978-996.

LOTRIČ, Uroš, BULIĆ, Patricio. Applicability of approximate multipliers in hardware neural networks. Neurocomputing (Amst.). [Print ed.], Nov. 2012, vol. 96, pp. 57-65, doi:10.1016/j.neucom.2011.09.039

BULIĆ, Patricio. Fixed-point multiplication and division in the logarithmic number system : a way to low-power design. Informacije MIDEM, ISSN 0352-9045, 2013, vol. 43, no. 4, pp. 203-211

RISOJEVIĆ Vladimir, AVRAMOVIĆ, Aleksej, BABIĆ, Zdenka, BULIĆ, Patricio A simple pipelined squaring circuit for DSP. V: 29th IEEE International Conference on Computer Design 2011, ICCD 2011, IEEE, cop. 2011

ČEŠNOVAR Rok, BULIĆ, Patricio, DOBRAVEC, Tomaž. Optimization of a single seam removal using a GPU. V: ARABNIA, PDPTA 2011 : proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications, Worldcomp'11, Las Vegas Nevada, USA

BABIĆ, Zdenka, AVRAMOVIĆ, Aleksej, BULIĆ, Patricio. An iterative logarithmic multiplier.Microprocess. microsyst.. [Print ed.], 2011, vol. 35, no. 1, str. 23-33, doi: 10.1016/j.micpro.2010.07.001.

BULIĆ, Patricio, GUŠTIN, Veselko, ŠONC, Damjan, ŠTRANCAR, Andrej. An FPGA-based integrated environment for computer architecture. Computer applications in engineering education, Mar. 2013, vol. 21, no. 1, str. 26-35

BULIĆ, Patricio, DOBRAVEC, Tomaž. An approximate method for filtering out data dependencies with a sufficiently large distance between memory references. J. supercomput., 2011, vol. 56, no. 2, str. 226-244, ilustr., doi: 10.1007/s11227-009-0364-8

BULIĆ, Patricio, BABIĆ, Zdenka, AVRAMOVIĆ, Aleksej. A simple pipelined logarithmic multiplier. V: 28th IEEE International Conference on Computer Design 2010, ICCD 2010 : embedded systems. [S. l.]: IEEE, cop. 2010, str. 235-240

GUŠTIN, Veselko, BULIĆ, Patricio. Learning computer architecture concepts with the FPGA-based "move" microprocessor. Comput. appl. eng. educ., 2006, vol. 14, no. 2, str. 135-14, doi: 10.1002/cae.20072.

BULIĆ, Patricio, GUŠTIN, Veselko. An extended ANSI C for processors with a multimedia extension. Int. j. parallel program., 2003, vol. 31, no. 2, str. 107-136, doi: 10.1023/A:1022617308483.